Conventional automatic test equipment (ATE) typically tests semiconductor devices according to a functional test scheme. This approach verifies that the device performs its intended function under a variety of realistic operating conditions. Use of the functional test approach often requires the generation of functional test patterns that exercise the device through its external interface.
As device complexities and densities increase, functional test costs tend to correspondingly increase. In particular, the volume of functional test pattern data required to achieve acceptable fault coverage may increase exponentially with the size of the device.
In an effort to lower these costs, many semiconductor manufacturers have employed structured design-for-test (DFT) and built-in-self-test (BIST) methods. With many of these test methods, the goal changes from verifying functionality to finding manufacturing defects. DFT and BIST methods generally rely on additional circuitry provided on the device to enhance the controllability and observability of the internal state of the device. In some cases, the resulting circuit may be adequately tested with lower-cost automatic test equipment.
While the art is replete with conventional standardized circuit schemes for digital DFT/BIST, the conventional approach to analog/mixed-signal DFT/BIST is far different. Conventionally, in order to implement and analyze test results for analog/mixed-signal circuit components such as analog-digital (A-D) converters, phase-locked-loops (PLL), digital-analog (D-A) converters, etc., using DFT/BIST techniques, different methods are typically implemented for each analog/mixed-signal circuit component. As a result, manufacturers have resorted to using custom ad-hoc analog/mixed-signal DFT methods (circuitry and software) to achieve desired results.
Generically, the conventional customized ad-hoc methods to approaching analog/mixed-signal DFT/BIST follow a common high-level scheme. Referring to FIG. 1, an analog or mixed-signal device-under-test (DUT) 10 includes one or more analog/mixed-signal circuits-under-test (CUT) 12. DFT/BIST circuitry employed in the DUT to test the CUT includes a drive/sense interface circuit 14 to sample and measure signals from the analog CUT and/or to drive signal into the CUT, and a digital load/capture circuit 16 to convert the sampled analog signals to digital signals and process the signals into a more useable format. Scan chain register circuitry 18 includes scan chain registers 20 that couple to the digital load/capture circuitry and TAP (Test Access Port) interface circuitry 22 to facilitate the transfer of data off the DUT to automatic test equipment (ATE) 30. Both TAP and or scan chain registers may be used to transfer data off of the DUT.
The ATE 30 often includes a host computer 32 that acts as a controller for one or more instruments 34. The instruments may include waveform digitizers, logic analyzers, etc., and are coupled conventionally in the tester as is well known to those skilled in the art. Conventionally, analog/mixed-signal DFT/BIST data is captured by digital instruments able to take advantage of the scan chain interface employed by the DUT 10. In operation, data from the analog/mixed-signal DFT/BIST circuitry that is acquired by the ATE digital instrument 34 is then fed to the ATE host computer 32 where it is processed and analyzed by vendor-supplied (or user-developed) custom analysis software algorithms tailored to the analog/mixed-signal DFT/BIST circuitry employed in the DUT 10.
As noted above, due to the ad-hoc nature of conventional analog/mixed-signal DFT/BIST methods, the circuitry and analysis software are typically customized for each type of analog/mixed-signal CUT and multiple analysis software may be needed if more than one type of DFT/BIST method is deployed on a given device. In other words, the DFT/BIST circuitry to test an A-D converter is different than that used to test a PLL, which is different than that to test D-A converters, etc. This lack of standardization often forces the semiconductor device manufacturer to implement custom analysis tools for each type of analog/mixed-signal CUT that translates into a higher cost of test for the semiconductor device manufacturer.
In addition to the ad-hoc methodology discussed above, conventional analog/mixed-signal DFT/BIST methods have often led to prolonged test times, often reducing device throughput, or required off-line analysis to determine pass/fail results which added to the cost of test. This is shown in FIG. 2, where, after each test of an analog/mixed-signal CUT 12, in steps 40, 44, and 48, the test is disrupted while the ATE host computer 32 directs its computing resources to analyzing the test results, at steps 42, 46, and 50. This stop and go test/analyze approach is undesirable to semiconductor manufacturers who value fast test rates in order to maximize device throughput. Some semiconductors manufacturers use off-line analysis to determine pass/fail in order to minimize the negative impact on the ATE. However, this method is also undesirable as it adds another process step and requires transfer of large amounts of data from the ATE to off-line storage.
What is needed and currently unavailable is a universal parallel processing approach to test and analyze DUTs that employ analog/mixed-signal DFT/BIST circuitry. The automatic test equipment analog/mixed-signal DFT/BIST apparatus and method of the present invention satisfies these needs.